The present invention relates generally to the fabrication of semiconductor devices, and more particularly, to semiconductor devices having through wafer vias for making electrical connections with other semiconductor components.
Modern semiconductor devices comprise of thousands or even millions of components (e.g., transistors, interconnects, pads, etc.) integrated into a single die. As customer demand improves chip performance, new requirements are placed on the die, and consequently the packaging that houses the die. Critical packaging parameters include the number of input and output (I/O) pins, electrical performance, thermal dissipation, and size.
Traditionally, after each good die is separated from the wafer, the die is attached to a package substrate or leadframe to provide electrical access to the die. Wirebonding is the most common method for electrically connecting bond pads on the chip surface to the package inner lead terminals on the package substrate. “Flip chip” is another way of connecting the die to the package substrate where the active side of the chip (with the surface bonding pads) is mounted toward the substrate (e.g., upside down placement of the bumped die relative to the wirebonding approach). An extension of flip chip, ball grid array (BGA), yet another way of attaching a die to the package substrate, uses flip chip C4 (controlled collapse chip carrier—developed by IBM in the 1960s) or wirebond technology.
However, these traditional approaches suffer from assembly and packaging challenges. Because the power and ground interconnections are typically connected from the bond pads on the top metals of the chip to the package substrate below, the circuit resistance is increased, which potentially increases the circuit length and the inter-electrode capacitance thus affecting the electrical performance. Due to these configurations, these packages typically require more power and increased I/O lead requirements leading to increased chip size and overall profile.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved semiconductor device and a method of manufacture thereof that addresses the above-discussed issues.